The incumbent will be focused on digital block verification of ASIC and FPGA device designs. The main goal of the tasks will be block verification to confirm that the functional requirements are fulfilled before release of the FPGA or type-out to ASIC.


- Responsible for verification planning and specification;
- Implement test case creation;
- Responsible for the usage of UVCs;
- Responsible for the creation of coverage matrix;
- Responsible for the creation of verification reports;
- Perform miscellaneous tasks in connection to the block design.

Required Qualifications:

- More than 5 years in IP HW verification experience using OVM/ UVM;
- Knowledge of verification methodologies fitted for FPGA and ASIC;
- Experience in system level verification;
- Experience in formal verification;
- Skills in VHDL programming language; skills in Verilog programming language will be considered a plus;
- Good programming skills in C;
- Excellent knowledge of English language (both written and verbal).

About Seavus

Seavus is an international software development and consulting company with a proven track-record in providing successful enterprise-wide business solutions. The company has over 650 IT experts worldwide and offers a variety of products and service options, successfully covering the European and US market from several offices in the world.
For more information please visit: http://seavus.com/ .