Overview

A&MS Layout Design Engineer

29006BR

ARMENIA – Yerevan

Job Description and Requirements

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.

A&MS Layout Design Engineer

We’re looking for a A&MS Layout Design Engineer to join the team.

Responsibilities:

-In this role you will collaborate in the development of advanced analog integrated circuit designs using best-in-class Synopsys suite of tools. You will be working with local and global teams in developing layout for complex mixed-signal designs in the latest technology nodes.
-As a member of our Solutions IP Design Group you will be developing IP in various technology nodes and foundries for different customers in a fast paced and exciting design environment.

Required Qualifications:

-In depth familiarity with layout of analog and mixed signal CMOS circuits,
-Knowledge of full custom analog layout design tool: Custom Compiler (or equivalent),
-Knowledge of verification tools: ICV, Calibre, Star-RCXT, PERC,
-Experience in working with Jira/Atlassian (or other such) tools,
-Strong working knowledge of MS Office Suite of applications,
-Exposure to scripting (ie. TCL, PERL, etc…).
-Preferred Experience
-Typically requires an MSEE or BSEE with a minimum of 2 years of related experience.
-Experience in development of SERDES subcircuit layout (ie. RX, TX, PLL, etc.
-Experience in the following layout design techniques:
-Optimization for signal integrity (ie. clock/data routes, differential routing, shielding)
-Implementation of ESD design constraints, latch-up risk mitigation
-Familiarity with custom digital layout (logic cell layout and associated logic path routing)
-Layout design for reliability (ie. EM, IR, etc…)
-Design to optimize for parasitic layout effects (ie. matching, reliability, proximity effects, etc…)
-Familiarity in design for porting techniques