Analog Design Manager
ARMENIA – Yerevan
Job Description and Requirements
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.
Analog Design Manager
We’re looking for a Analog Design Manager to join the team. Does this sound like a good role for you?
In this role, you will guide a team performing timing characterization of SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team developing high speed analog integrated circuits in the latest FinFET CMOS processes. We are looking for a manager with theoretical knowledge and practical experience to contribute to the team. You will work with a cross functional design team of analog, digital and top level integration designers from a wide variety of backgrounds. Our design environment is best-in-class with a full suite of IC design tools, supplemented by custom in-house tools, and supported by an experienced software/CAD team.
-Direct and guide the activities of a team of engineers characterizing timing, analysis timing results, and generating timing models of high-speed SERDES IP.
-Develop and align timing flow and methodology to ensure efficiency and quality of the team’s deliverables.
-Conduct design reviews and evaluate final results of timing views and reports.
-Present results of timing, assessments or critical issue investigation and make recommendation for actions necessary to achieve desired results.
-Ensure the team follows processes for maximum design quality.
-Consult on the timing charactersitcs of the SerDes Ip product.
-Propose solutions for STA timing closure.
-MSc with 5 years experience of IC design.
-Familiarity with transistor level circuit design and CMOS design fundamentals.
-In depth knowledge of setup and hold timing analysis.
-Detailed experience timing characterization, modelling, simulation and verification.
-Familiarity with custom digital design (i.e. high speed logic paths).
-Experience with tools for timing experience, for example, Primetime, Nanotime, or equivalent.
-Hands-on experience with physical layout of high speed circuits is a plus.
-Knowledge of SPICE simulators and simulation methods.
-Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired.
-Good communication and documentation skills.