Overview

We’re looking for ASIC Physical Design Engineer to join the team.

Requisition Number: 25773BR

ARMENIA – Yerevan

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.

Responsibilities:

-In this role you will be responsible of implementing RTLIIGDS flow, which includes following stages:
-Gate level netlist synthesis
-Physical implementation
-Formal verification
-STA
-Physical verification
-Signoff

Required Qualifications:

-Key Qualifications

-Requires a degree in Electrical or Computer Engineering with specialization in Micro-electronics (or equivalent)
-Possesses relevant experience in deep submicron CMOS technologies.
-Knowledge of the full design cycle from RTL to GDSII

-Has academic and practical exposure in following fields
-high-speed design
-low-power design
-high speed clock design and distribution
-timing closure
-signal integrity

-Good software and scripting skills; knowledge of CAD automation methods.
-Good written and verbal communication in English
-Teamwork or Network relation experiences
-Problem-solving and organizational skills.

-Preferred Experience

-2+ years of relevant work experience.
-ASIC design methodology experience in back end flows of digital and Mixed Signal circuit design.
-Knowledge of design for porting across multiple foundry nodes