We’re looking for ASIC Physical Design Engineer to join the team.
Requisition Number: 25778BR
ARMENIA – Yerevan
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
-In this role you'll be responsible for floor-planning, signal integrity avoidance, analysis and manufacturing verification. The individual will contribute in the implementation and technology re-targeting for a variety of mixed signal IP products which will require close interaction and collaborative team work with multiple functional groups (front end, analog, application).
-has experience between 0 and 2 years.
-has engineering understanding of the underlying concepts of IC design.
-has knowledge of the full design cycle from RTL to GDSII.
-has academic and practical exposure in high performance digital design and CAD, high-speed design, low-power design, high speed clock design and distribution, timing closure, signal integrity.
-has good software and scripting skills; knowledge of CAD automation methods.
-has English speaking level allowing interaction with the larger product team to understand design constraints, deliverable formats, and customer requirements.
-be able to follow defined design methodologies and processes to implement and deliver on schedule.
-be responsible for floor-planning,
-be responsible for physical synthesis, clock tree generation, routing, extraction, timing closure,
-identify signal integrity avoidance, analyze and repair.
-contribute in the implementation and technology re-targeting for a variety of mixed signal IP products and test-chips at 32nm, 28 and below.