Overview
Responsibilities:
- development of IFS/GUI according to technical specifications
- design and implementation of verification IPs and test-benches
- testing and debugging Verilog RTL
- creation and review of design verification documentation
- communicate effectively with team members
Required Qualifications:
- experience in Unix environments
- familiarity with VLSI design flow, FPGA architecture and FPGA tools flows
- basic knowledge of TCL/Python scripting languages
- knowledge of C++/QT
- knowledge of Verilog HDL
- ability to quickly learn new languages and study documentation
- good communication skills in English
- teamwork skills
