Junior FPGA Logical Verification Engineer

Familiarity on RTL Verification

Familiarity on digital fundamentals and understanding of FPGA/ custom chip flow

Knowledge on Verilog and SystemVerilog, UVM

Knowledge on C/C++ language

Familiarity with FPGA programming and related software usage with Firmware handling knowledge is a plus

Experience with UNIX shell scripting or Perl scripting

Good analytical and problem solving skills

Good written and verbal communication in English.