Senior Analog Design Engineer
ARMENIA – Yerevan
Job Description and Requirements
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.
Inclusion and Diversity are important to us. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, age, military veteran status, or disability.
-In this role you will review SerDes standards and architecture documents to develop analog sub-block specifications. Identify and refine circuit implementations to achieve optimal power, area and performance targets. The job responsibilities also include:
-Proposing design and verification strategies that efficiently use simulator features to ensure highest quality design
-Overseeing physical layout to minimize the effect of parasitics, device stress, and process variation
-Collaborating with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits
-Presenting simulation data for peer and customer review
-Mentoring and reviewing the progress of junior engineers
-Documenting design features and test plans
-Consulting on the electrical characterization of your circuit within the SerDes IP product
-8+ years of SerDes/High-Speed analog design experience
-In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals
-Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.)
-Knowledge of SPICE simulators and simulation methods
-Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture
-Silicon-proven experience implementing circuits for the TX, RX and Clock paths within a SerDes
-Detailed design experience with several of the following SerDes sub-circuits: receive equalizers, data samplers, voltage/current-mode drivers, serializers, deserializers, voltage-controlled oscillator, phase interpolator, delay-locked loop, phase-locked loop, bandgap reference, ADC, DAC
-Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects
-Experience with EDA tools for schematic entry, physical layout, and design verification
-Experience with TCL, Perl, C, Python, MATLAB