Senior Analog Design Engineer


ARMENIA – Yerevan

Job Description and Requirements

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.

Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk.

Senior Analog Design Engineer

We're looking for Senior Analog Design Engineer to join our team.

Does this sound like a good role for you?

You will be part of an R&D team developing high speed analog and mixed-signal integrated circuits for high speed SerDes IP. We are looking for an engineer with theoretical knowledge and practical experience to contribute to the team. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our design environment is best-in-class with a full suite of IC design tools, supplemented by custom in-house tools, and supported by an experienced software/CAD team.



Required Qualifications:

MSc with 3 years’ experience of IC design
Familiarity with transistor level circuit design and CMOS design fundamentals
In depth knowledge of setup and hold timing analysis
Detailed experience timing characterization, modelling, simulation and verification
Familiarity with custom digital design (i.e. high speed logic paths)
Experience with tools for timing experience, for example, Primetime, Nanotime, or equivalent
Hands-on experience with physical layout of high speed circuits is a plus
Knowledge of SPICE simulators and simulation methods
Experience with TCL, Perl, C, Python, MATLAB, or other scripting languages is desired
Good communication and documentation skills
Preferred Experience
Characterize timing, analyze timing results, and generate timing models of high-speed SERDES IP
Align timing flow and methodology to deliver timing models with high efficiency and quality
Present results of timing, assessments or critical issue investigation and follow appropriate actions necessary to achieve desired results