Sr Analog Design Engineer
ARMENIA – Yerevan
Job Description and Requirements
At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Our Silicon Design & Verification business is all about building high-performance silicon chips—faster. We’re the world’s leading provider of solutions for designing and verifying advanced silicon chips. And we design the next-generation processes and models needed to manufacture those chips. We enable our customers to optimize chips for power, cost, and performance—eliminating months off their project schedules.
Sr Analog Circuit Design Engineer
We’re looking for an A&MS Circuit Design Engineer to join the team. Does this sound like a good role for you?
In this role you will review SerDes standards and architecture documents to develop analog sub-block specifications. Identify and refine circuit implementations to achieve optimal power, area and performance targets.
-Review SerDes standards and architecture documents to develop analog sub-block specifications.
-Identify and refine circuit implementations to achieve optimal power, area and performance targets.
-Propose design and verification strategies that efficiently use simulator features to ensure highest quality design.
-Oversee physical layout to minimize the effect of parasitics, device stress, and process variation.
-Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits.
-Present simulation data for peer and customer review.
-Mentor and Review the progress of junior engineers.
-Document design features and test plans.
-Consult on the electrical characterization of your circuit within the SerDes IP product.
-MD or PhD with 5+ years of A&MS design experience.
-Awareness of custom design flow’s details.
-In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals.
-Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects.
-Awareness of ESD issues (i.e. circuit techniques, layout). and design for reliability (i.e. electro-migration, IR, aging, etc.).
-Experience with EDA tools for schematic entry, physical layout, and design verification.
-Knowledge of SPICE simulators and simulation methods.
-Knowledgeable in Verilog-A for analog behavioral modeling and simulation-control/data-capture.
-Experience with TCL, Perl, C, Python, MATLAB.