“Rushc LLC” is looking for a “Static Timing Analysis Engineer”.


Develop static timing analysis engine for new chip using C++ and Qt. Includes clock propagation, edge propagation, on chip variation, clock recovery.

Required Qualifications:

Education and Experience:
- Master’s in electrical engineering
- 5 years EDA development (Synopsys preferred) Required Knowledge:
- Knowledge of SDC constraints, edge propagation, timing analysis techniques
- Graph theory knowledge (traversals, strongly connected components algorithm, Dfs, bfs)
- Knowledge of liberty library, sdf, verilog formats
- Strong C++ skills