Overview

Join a dynamic group dedicated to ensuring robust test infrastructure for cutting-edge hardware solutions. Our team collaborates closely with design and product development teams, playing a pivotal role in the integration and validation of test logic throughout the development lifecycle.

Responsibilities:
  • Drive comprehensive test planning and develop advanced test benches to ensure design integrity.
  • Collaborate with cross-functional teams to integrate and validate test logic at every phase of implementation.
  • Utilize scripting and debugging tools to streamline verification workflows and identify issues efficiently.
  • Apply your expertise to optimize test processes and enhance product quality.
  • Deliver critical verification solutions that directly impact the success and reliability of our products.
Required Qualifications:
  • Bachelor’s or Master’s Degree in Electrical or Computer Engineering or any related field.
  • 7+ years of experience in design verification.
  • Prior experience in test planning based on complex design specifications.
  • Proficiency in testbench development using System Verilog.
  • Debugging experience preferably using DVE and Verdi.
  • Strong scripting skills with at least one of Tcl, Python and Perl.
  • Knowledge of constrained-random verification and functional coverage.
  • Knowledge of ASIC design flow and verification methodologies.
Nice To Have:
  • UVM and advanced System Verilog knowledge.
  • Knowledge of JTAG protocol.
  • Familiarity with SLM IP and verification strategies.
  • Ability to work effectively in cross-functional teams.
  • Strong analytical and problem-solving skills.
  • Good communication skills and ability to work in a team environment.
Skills:
  • Test Planning
  • Testbench Development
  • Debugging
  • Constrained-Random Verification
  • Functional Coverage
  • ASIC Design Flow
  • Verification Methodologies
  • Problem-Solving
Technologies:
  • System Verilog
  • DVE
  • Verdi
  • Tcl
  • Python
  • Perl
  • UVM
  • JTAG
  • SLM IP
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