Overview

Our team specializes in macro-level RTL-to-GDSII physical implementation and signoff, collaborating closely with Front-End teams to ensure optimal results. We are dedicated to delivering complex SoC and block-level projects through technical excellence and teamwork. The team is composed of highly experienced professionals who value collaboration and high standards in physical design.

Responsibilities:
  • Lead macro-level RTL-to-GDSII physical implementation and signoff.
  • Collaborate with Front-End teams to translate architecture into optimal physical design.
  • Perform synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing.
  • Optimize power, performance, and area (PPA) while maintaining design correctness through formal verification.
  • Execute static timing analysis (STA), physical verification, formal checks, and signoff closure to ensure reliable, high-quality silicon.
  • Analyze and resolve Electromigration (EM) and IR-drop issues to meet reliability and performance signoff targets.
Required Qualifications:
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field.
  • 5+ years of hands-on experience in ASIC design and physical implementation.
  • Proven track record in ASIC physical design and verification preferably in complex SoC or block-level projects.
  • Deep knowledge of block-level synthesis, place-and-route (PnR), and timing closure.
  • Experience with industry-standard PnR and signoff tools (e.g., Synopsys, Cadence).
Nice To Have:
  • Broad understanding of physical design methodologies, integration, and implementation flows.
  • Experience in physical verification (LVS, DRC) and signoff processes.
  • Familiarity with physical design EDA toolchains and end-to-end workflows.
  • Advanced expertise in STA, timing closure, and constraint management.
  • Proficiency in scripting (Tcl, Python, or Perl) for automation and productivity improvements.
Technologies:
  • Synopsys
  • Cadence
  • Tcl
  • Python
  • Perl
Note:

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