Overview

Join Cisco’s ASIC Design for Test (DFT) Team, where innovation, collaboration, and technical excellence drive everything we do.

Responsibilities:
  • Architect and Implement DFT Solutions: Design and integrate advanced Test Access Mechanisms (TAM), scan chains, Built-In Self-Test (BIST), and Memory BIST (MBIST) infrastructures for complex integrated circuits.
  • Test Planning and Coverage Analysis: Lead test planning, test pattern generation, and fault coverage analysis to improve test coverage for both digital and mixed-signal designs.
  • Collaborate Across Teams: Work closely with design, verification, ATE, and physical design teams to ensure DFT structures meet functional, timing, and implementation requirements.
  • Leverage Tools and Automation: Apply and develop automation scripts and in-house tools for DFT workflows, including MBIST pattern generation and fault simulation, using industry-standard EDA solutions.
  • Fault Diagnosis and Debugging: Identify, analyze, and debug issues related to DFT structures, perform root cause analysis on failed tests, and recommend design changes for improved testability.
  • Documentation and Reporting: Prepare detailed documentation on test plans, test coverage, and debugging results; report on DFT metrics to ensure compliance with company and industry standards.
Required Qualifications:
  • Bachelor’s or higher degree in Electrical Engineering, Computer Engineering, or a related technical field.
  • 2+ years of hands-on experience in MBIST, SCAN/ATPG, and DFT methodologies for complex digital and mixed-signal designs.
  • Proven expertise with industry-standard DFT tools and flows (e.g., Synopsys, Cadence, Mentor).
  • Strong understanding of ASIC/FPGA design flow, including RTL design, verification, and test.
  • Proficiency in scripting languages such as Tcl, Python, or Perl for test automation and workflow enhancement.
  • Demonstrated ability to identify, analyze, and resolve DFT issues related to MBIST insertion, pattern generation, and fault coverage.
  • Excellent communication skills and experience collaborating within cross-functional engineering teams.
Nice To Have:
  • Expertise in advanced DFT methodologies such as Logic BIST, Memory BIST, and hybrid scan/MBIST approaches.
  • Experience with low-power DFT strategies and power-aware test techniques.
  • Ability to develop custom scripts or internal tools for DFT analysis and automation.
  • Familiarity with industry standards such as IEEE 1149.1 (JTAG) and IEEE 1500.
  • Experience leading DFT efforts on large-scale projects and mentoring junior engineers.
  • Strong project management skills and a track record of driving test planning and implementation best practices.
Skills:
  • Tcl
  • Python
  • Perl
  • ASIC/FPGA design flow
  • RTL design
  • verification
  • DFT methodologies
Technologies:
  • Synopsys
  • Cadence
  • Mentor
  • MBIST
  • SCAN/ATPG
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