Overview

Our team is at the forefront of innovation, specializing in memory layout implementation for the Cisco Silicon One platform that powers the world’s most advanced switches and routers.

Responsibilities:
  • Implement high-quality memory layout implementation, specifically focusing on SRAM blocks to meet rigorous performance and reliability standards
  • Collaborate closely with international circuit design teams to translate schematics into robust physical designs that drive our core networking products
  • Perform post-layout simulations and implement necessary corrections to ensure DRC cleanliness and optimal integration with neighboring modules
  • Optimize layout designs for quality, visibility, and velocity to accelerate the delivery of critical silicon components
Required Qualifications:
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field
  • 5+ years of total professional experience in physical design or layout
  • 3+ years of hands-on experience specifically in SRAM layout implementation
  • Proven experience working with industry-standard EDA tools such as Cadence or Synopsys
  • Experience with advanced node technologies such as TSMC 22nm, 12nm, 7nm, 5nm, or 2nm
Nice To Have:
  • Experience working within a mixed-signal or custom design environment
  • Proficiency in performing EMIR/ERC closure and providing technical support for successful tapeouts
  • Background in circuit design, including reading schematics and running simulations
  • Proficiency in scripting languages (Tcl, Python, or Perl) for design automation
  • Strong ability to communicate effectively in English, both written and spoken, to support international collaboration
  • Demonstrated ability to work both independently and within a cross-functional, multi-site team environment
Technologies:
  • Cadence
  • Synopsys
  • TSMC 22nm
  • 12nm
  • 7nm
  • 5nm
  • 2nm
  • Tcl
  • Python
  • Perl
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