Job Description

We are hiring an ASIC Engineer to design and verify standard cells for our next-generation ASICs on innovative FinFET and GAA nodes. You will build high-performance cell layouts, take them to clean physical verification, and run library QA checks before release. You will work closely with senior engineers and with the circuit design, characterization and physical design teams. This role offers broad hands-on exposure and a clear path to technical ownership.

Responsibilities:
  • Design standard cell layouts: logic, high-drive, clock, level shifter, tap/boundary and specialty cells.
  • Optimize cell layouts for density, performance, power, EM and manufacturability.
  • Run physical verification and fix issues to clean signoff: DRC, LVS, antenna, ERC and extraction.
  • Run library QA checks and resolve view mismatches across GDS, LEF, Liberty, NDM and CDL.
  • Develop and maintain scripts for layout, verification and QA (Python, Tcl, SKILL).
  • Support analog/mixed-signal layout work with the mixed-signal team.
  • Support the characterization team with extraction and netlist QA, and help prepare library releases.
  • Debug block-level layout and verification issues with the physical design and STA teams.
  • Take part in layout and QA reviews and contribute to methodology improvements.
Required Qualifications:
  • Bachelor's + 3 years, Master's + 2 years, or PhD of related experience in Electrical Engineering, Computer Engineering or a related field.
  • First hand standard cell or custom layout experience on FinFET nodes such as TSMC 7nm, 5nm, 3nm or 2nm.
  • Experience with physical verification and extraction tools such as Calibre, ICV, StarRC or Quantus.
  • Proficiency in Cadence Virtuoso.
Nice To Have:
  • Analog/mixed-signal design and layout experience, such as PLLs, LDOs, bandgaps, IOs or sensors, including matching, shielding and post-layout simulation.
  • Experience with standard cell characterization and Liberty modeling, using tools such as PrimeLib, Liberate or SiliconSmart.
  • Experience with library QA and view consistency checks (GDS, LEF, Liberty, CDL).
  • Exposure to library release: abstract/LEF and NDM generation and validation in P&R tools.
  • Scripting in Python, Tcl, SKILL or Perl for design automation.
  • Familiarity with EM/IR analysis and low-power cells (multi-Vt, power gating, retention).
  • Strong written and spoken English, and experience working in multi-site teams.
Technologies:
  • Python
  • Tcl
  • SKILL
  • Calibre
  • ICV
  • StarRC
  • Quantus
  • Cadence Virtuoso
  • PrimeLib
  • Liberate
  • SiliconSmart
  • Perl
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