Job Description

As part of the team behind Cisco Silicon One—the industry’s only unified silicon architecture spanning top-of-rack switches to web-scale data centers—you’ll help shape Cisco’s groundbreaking solutions by designing, developing, and testing some of the most advanced ASICs in the industry. Our international group focuses on groundbreaking process technology to ensure the efficiency and performance of our ASIC products.

Responsibilities:
  • Drive the architecture, design, and implementation of high-performance ASIC subsystems and IP from specification through silicon validation.
  • Develop and productize standard-cell, custom digital, and analog/mixed-signal IP to meet strict performance and robustness requirements.
  • Perform transistor-level simulation and optimization, accounting for process, voltage, temperature, and aging conditions.
  • Define and implement characterization methodologies for standard-cell and mixed-signal models, including the deployment of automated EDA flows.
  • Collaborate with multi-functional teams, including physical design and system architecture, to define interface requirements and implementation constraints.
  • Own the physical implementation of complex custom blocks, optimizing for timing, power, signal integrity, and layout-dependent effects.
  • Analyze silicon results post-bring-up to drive improvements in circuit design, characterization models, and future IP architectures.
  • Drive technical reviews for schematics, layouts, and methodologies to resolve complex cross-disciplinary issues and mitigate architectural risks.
  • Develop reusable infrastructure, scripts, and documentation to improve engineering productivity and design quality.
  • Apply expertise in advanced process nodes, including FinFET and GAA, to push the boundaries of ASIC power-delivery and clocking solutions.
Required Qualifications:
  • Bachelor’s degree and 7 years of related experience, or Master’s degree plus 4 years of related experience, or PhD plus 1 year of related experience.
  • Relevant experience should include ASIC, custom digital, standard-cell, or analog/mixed-signal circuit design and implementation.
Nice To Have:
  • Design & IP Development: Proven expertise in designing and optimizing custom digital circuits (e.g., standard cells, low-power cells) and analog/mixed-signal IP (e.g., regulators, oscillators, sensors) with a strict focus on PPA, reliability, and yield.
  • Methodology & Analysis: Strong background in circuit-level analysis (SPICE, PVT, Monte Carlo, variation) and standard-cell modeling (Liberty, CCS/ECSM, LVF) using industry-standard EDA tools from Cadence, Synopsys, or Siemens.
  • Physical & Process Implementation: First-hand experience with advanced nodes (FinFET/GAA) and physical implementation flows, including custom layout, parasitic extraction, DRC/LVS, and reliability analysis (EM/IR).
  • Silicon Lifecycle & Leadership: Demonstrated ability to lead technical reviews, influence ASIC architecture, and get results through silicon bring-up, failure analysis, and model-to-silicon correlation.
  • Proficiency in automation and scripting (Python, Tcl, or shell) to enhance engineering productivity.
Skills:
  • ASIC
  • Circuit Design
  • Custom Digital
  • Analog/Mixed-Signal
  • Physical Design
  • Silicon Validation
Technologies:
  • Python
  • Tcl
  • SPICE
  • Cadence
  • Synopsys
  • Siemens
Note:

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