Overview

Our team is dedicated to advancing DFT architecture to ensure robust test planning and development that supports ATE screening, in-system testing, debugging, and diagnostics. We collaborate closely with design, design-verification, and product development teams to integrate and validate test logic throughout implementation and post-silicon validation phases. Comprising experienced engineers passionate about innovation, our team fosters a collaborative and dynamic environment focused on developing reusable test and debug methodologies for new silicon device models, including bare die and stacked die. What excites us most is driving cutting-edge hardware DFT strategies and solving complex challenges that directly impact the quality and reliability of Cisco’s silicon products.

Responsibilities:
  • Lead the development and execution of comprehensive test benches to verify DFT architectures, ensuring thorough coverage of design specifications.
  • Collaborate cross-functionally to integrate test logic and validate it across all implementation stages and post-silicon validation flows.
  • Drive innovation in hardware DFT and test strategies for emerging silicon device models, promoting reusable methodologies and standards.
  • Identify DFT challenges, facilitate solution brainstorming, and develop implementation plans while mentoring junior engineers to meet project timelines.
  • Your work will directly enhance test coverage, debug efficiency, and product quality, making a significant impact on Cisco’s silicon design and validation processes.
Required Qualifications:
  • Bachelor’s or Master’s Degree in Electrical, Computer Engineering or any relevant field.
  • 10+ years of experience in design verification or ASIC design.
  • Proven experience in test planning based on complex design specifications.
  • Proficiency in debugging using DVE/Verdi tools.
  • Experience in scripting languages like Tcl, Python, or Perl.
Nice To Have:
  • Experience in testbench development using SystemVerilog.
  • Knowledge of JTAG protocol, scan architecture, MBIST, and boundary scan.
  • Familiarity with innovative hardware DFT and test strategy development.
  • Ability to lead and mentor engineers.
  • Strong problem-solving skills with minimal mentorship.
Skills:
  • Test Planning
  • Debugging
  • Hardware DFT
  • Test Strategy
  • Leadership
  • Mentoring
  • Problem-solving
Technologies:
  • DVE
  • Verdi
  • Tcl
  • Python
  • Perl
  • SystemVerilog
  • JTAG
  • MBIST
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