Job Description

Lead macro-level RTL-to-GDSII physical implementation and signoff. Collaborate with Front-End teams to translate architecture into optimal physical design. Perform synthesis, floorplanning, placement, Clock Tree Synthesis, and routing. Optimize power, performance, and area while maintaining design correctness through formal verification. Execute static timing analysis, physical verification, formal checks, and signoff closure to ensure reliable, high-quality silicon. Analyze and resolve Electromigration and IR-drop issues to meet reliability and performance signoff targets.

Responsibilities:
  • Lead macro-level RTL-to-GDSII physical implementation and signoff
  • Collaborate with Front-End teams to translate architecture into optimal physical design
  • Perform synthesis, floorplanning, placement, Clock Tree Synthesis, and routing
  • Optimize power, performance, and area while maintaining design correctness through formal verification
  • Execute static timing analysis, physical verification, formal checks, and signoff closure
  • Ensure reliable, high-quality silicon
  • Analyze and resolve Electromigration and IR-drop issues to meet reliability and performance signoff targets
Required Qualifications:
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Science, or a related field
  • 5+ years of hands-on experience in ASIC design and physical implementation
  • Proven track record in ASIC physical design and verification preferably in complex SoC or block-level projects
  • Deep knowledge of block-level synthesis, place-and-route (PnR), and timing closure
  • Experience with industry-standard PnR and signoff tools (e.g., Synopsys, Cadence)
Benefits:
  • Innovative hardware platforms central to the AI era
  • Global team of creative experts
  • Full product development from design to qualification to production within the team
  • Opportunities to grow and build
  • Collaborative environment with empathy
  • Global impact through innovative solutions
Nice To Have:
  • Broad understanding of physical design methodologies, integration, and implementation flows
  • Experience in physical verification (LVS, DRC) and signoff processes
  • Familiarity with physical design EDA toolchains and end-to-end workflows
  • Advanced expertise in STA, timing closure, and constraint management
  • Proficiency in scripting (Tcl, Python, or Perl) for automation and productivity improvements
Skills:
  • ASIC design and physical implementation
  • Block-level synthesis, place-and-route (PnR), and timing closure
  • Physical verification (LVS, DRC)
  • Formal verification and signoff processes
  • Advanced static timing analysis (STA)
  • Constraint management
  • Automation and productivity scripting (Tcl, Python, Perl)
Technologies:
  • Synopsys tools
  • Cadence tools
  • Physical design EDA toolchains
Note:

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