Overview

Join our innovative ASIC Verification team, dedicated to ensuring the reliability and functionality of advanced digital designs. Our work is integral to delivering high-quality solutions that power next-generation products across the organization. The team is comprised of experienced engineers with diverse backgrounds, fostering a collaborative and energetic environment. We thrive on tackling challenging projects and leveraging the latest verification methodologies. With a strong focus on continuous learning and technical excellence, this team offers a dynamic and exciting place to grow your career.

Responsibilities:
  • Drive comprehensive test planning and development of robust test benches to support cutting-edge ASIC projects
  • Collaborate closely with design, design-verification, and physical design (PD) teams to integrate and validate test logic throughout all phases of implementation
  • Identify and resolve technical issues by leveraging advanced debugging tools and scripting skills
  • Develop and refine verification strategies to ensure optimal coverage and efficiency
  • Contribute to delivering high-quality, reliable products that advance technology and innovation
Required Qualifications:
  • Bachelor’s or Master’s Degree in Electrical or Computer Engineering or any related field
  • 2+ years of experience in design verification
  • Demonstrated experience in test planning based on complex design specifications
  • Proven expertise in testbench development using System Verilog
  • Hands-on debugging experience preferably with DVE and Verdi tools
  • Proficiency in scripting languages with at least one of Tcl, Python, or Perl
Nice To Have:
  • Knowledge of UVM and System Verilog
  • Experience adapting verification strategies for AI calibration and emerging technologies
Skills:
  • Strong problem-solving and analytical skills
  • Ability to work effectively in cross-functional teams
  • Good communication skills and ability to work in a team environment
Technologies:
  • System Verilog
  • DVE
  • Verdi
  • Tcl
  • Python
  • Perl
  • UVM
Note:

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