Overview

Join our dynamic Test Timing Engineering team, a group of passionate experts dedicated to ensuring robust and accurate timing constraints for advanced chip designs. Our work is critical to the success of the broader silicon design process, enabling efficient test and verification of complex integrated circuits. The team is mid-sized, blending seasoned engineers with fresh perspectives, fostering a collaborative and supportive environment. You’ll find an atmosphere of innovation, continuous learning, and strong cross-functional collaboration, all driven by a commitment to technical excellence.

Responsibilities:
  • Own the creation and validation of timing constraints at block, sub-chip, and full-chip levels in various test modes.
  • Perform quality checks, including identifying duplicated constraints and verifying unconstrained endpoints, to drive robust timing analysis.
  • Develop and enhance methodologies, guidelines, and checklists to streamline static timing analysis (STA) workflows.
  • Collaborate with cross-functional teams to resolve timing and design flow issues, accelerating project execution.
  • Implement and maintain SDC flows and validation processes to ensure compliance and accuracy across all design stages.
Required Qualifications:
  • Bachelor’s degree in electrical or computer engineering (or equivalent field) with 8+ years of relevant work experience or Master’s degree in electrical or computer engineering (or equivalent) with 6+ years of relevant experience.
  • Demonstrated experience developing block/full-chip SDC in test modes (scan shift, scan capture, ATPG capture).
  • Proficiency in Static Timing Analysis (STA) and hands-on experience with tools such as PrimeTime.
  • Programming proficiency in at least two scripting languages (e.g., Perl, TCL, Python, Makefile).
  • Proven track record in SDC validation, timing exception handling, and STA flow development.
Benefits:
  • Revolutionizing data and infrastructure connections in the AI era
  • Innovative solutions that power human-technology collaboration across physical and digital worlds
  • Unparalleled security, visibility, and insights across the entire digital footprint
  • Global network of experts and opportunities for growth and innovation
  • Collaborative work environment with empathy and global impact
Nice To Have:
  • Master’s degree in electrical or computer engineering (or equivalent) with 6+ years of relevant experience.
  • Experience debugging and analyzing timing constraints for DFT modes (scan shift/capture, BIST)
  • Prior hands-on experience with SDC debugging and STA tools (Synopsys GCA/TCM/PrimeTime)
  • Experience with synthesis tools, especially Synopsys Fusion Compiler, and Tessent DFT insertion
  • Strong communication skills and proven ability to work collaboratively within cross-functional teams
Skills:
  • Static Timing Analysis (STA)
  • SDC (Synopsys Design Constraints) development
  • Timing constraint validation
  • Scripting languages (Perl, TCL, Python, Makefile)
  • Cross-functional collaboration
  • Problem-solving and technical excellence
Technologies:
  • PrimeTime
  • Synopsys GCA/TCM
  • Synopsys Fusion Compiler
  • Tessent DFT insertion
Note:

✨ Our intelligent job search engine discovered this job and republished it for your convenience.
Please be aware that the job information may be incorrect or incomplete. The job announcement remains the property of its original publisher. To view the original job and its full details, please visit the job's URL on the owner’s page.

Please clearly mention that you have heard of this job opportunity on https://ijob.am.